The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), which may be realized as metal oxide semiconductor field effect transistors (MOSFETs or MOS transistors). A MOS transistor may be realized as a p-type device (i.e., a PMOS transistor) or an n-type device (i.e., an NMOS transistor). Moreover, a semiconductor device can include both PMOS and NMOS transistors, and such a device is commonly referred to as a complementary MOS or CMOS device. A MOS transistor includes a gate electrode as a control electrode that is formed over a semiconductor substrate, and spaced-apart source and drain regions formed within the semiconductor substrate and between which a current can flow. The source and drain regions are typically accessed via respective conductive contacts formed on the source and drain regions. Bias voltages applied to the gate electrode, the source contact, and the drain contact control the flow of current through a channel in the semiconductor substrate between the source and drain regions beneath the gate electrode. Conductive metal interconnects (plugs) formed in an insulating layer are typically used to deliver bias voltages to the gate, source, and drain contacts.
A conductive interconnect arrangement or architecture can be utilized to interconnect the many transistors that typically form an integrated circuit. Patterned metal layers, which are formed overlying the uppermost metal contact layer used to form the source, drain, and gate contacts of the transistors, are commonly used to create an interconnect arrangement. The different metal interconnect layers are separated by dielectric material (an interlayer dielectric or ILD). At a given interconnect level, patterned trenches are filled with conductive metal material to create the desired interconnect routing. Conductive plugs (typically formed from a tungsten-based material) are used to establish electrical contact between an interconnect trace to an underlying doped region, gate electrode, or lower interconnecting level.
Interconnect structures are often created with insulating materials having very low dielectric constants (e.g., ultra-low-k (ULK) materials). ULK materials are desirable to reduce capacitive coupling between neighboring conductive layers or structures. Unfortunately, existing processes for creating interconnect structures with ULK material can be time consuming, costly, and overly complex.
Accordingly, it is desirable to have an improved fabrication process that can be used to create an interconnect arrangement for a semiconductor device in an efficient, simple, and economical manner. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.